The Exelixis Lab


Enabling Research in Evolutionary Biology

Reconfigurable Architectures

Also look at opencores for latest updates

Reconfigurable FPGA Pipelined Floating-Point Exponential Unit available here

Source code under GNU GPL version 3 or higher by Nikos Alachiotis. The following restriction to GNU GPL applies: Always cite:

Nikos Alachiotis, Alexandros Stamatakis: "FPGA Optimizations for a Pipelined Floating-Point Exponential Unit", accepted for publication, 7th International Symposium on Applied Reconfigurable Computing (ARC 2011), Belfast, United Kingdom, March 2011.

when using this code.

An IEEE-754 compliant logarithm approximation unit for FPGAs by Nikos Alachiotis

Download an open-source VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs.

By using this component you agree to cite this paper: "Efficient Floating-Point Logarithm Unit for FPGAs", by Nikos Alachiotis and Alexandros Stamatakis, RAW workhsop proceedings, held in conjunction with IPDPS 2010. PDF and also this paper.

UDP Transceiver Core by Nikos Alachiotis and Simon A. Berger

Download an open-source VHDL implementation of a component that can be connected to the input port of the Virtex-5 Ethernet MAC Local Link Wrapper and that allows for transceiving IPv4 ethernet packets. The archive contains a JAVA test application and is also available at opencores.org.

By using this component, you agree to cite the following two papers: paper and paper 2

An exponential unit for FPGAs by Nikos Alachiotis

Download the source code that is distributed under GNU GPL version 3 or higher by Nikos Alachiotis. The following restriction to GNU GPL applies: Always cite the following paper:

Nikos Alachiotis, Alexandros Stamatakis: "FPGA Optimizations for a Pipelined Floating-Point Exponential Unit", 7th International Symposium on Applied Reconfigurable Computing (ARC 2011), Belfast, United Kingdom, March 2011.

when using this code.